CS/EE 5830/6830
VLSI Architecture
Spring 2011



General Information

Important Information

Course Description

In general VLSI Archtitecture is a class that looks in depth at a particular application domain and how that domain interacts with VLSI implementation. This year we'll be looking at Arithmetic circuits and systems. We will look in detail at arithmetic subsystems and do projects based on studying and characterizing the behavior (speed, power, size, etc.) of various arithmetic subsystems for VLSI.

Grading

Grading will be based on participation. Note that grad students registered for 6830 will be expected to read and evaluate two additional papers so the grading scale is slightly different for 6830. Expected participation includes:

Notice that although this is a project-based class, 20% of the total grade is based on writing about your results! Plan now to spend to spend some time preparing a nice final paper and report document!

For the final project, all team members will receive the same grade. However, there will be a chance at the end of the semester for all team members to confidentially evaluate the contribution made by their teammates to the project. If there is enough evidence that a team member did not contribute effectively to the project, I may reduce that team member's project score to account for this.

There will be some additional assignments for CS/EE6830 students involving reading, summarizing, and possibly presenting papers related to the subject of the course.

Digital VLSI Chip Design using Cadence and Synopsys CAD Tools

We'll be using CAD tools from Cadence and Synopsys this semester. These are "industrial strength" CAD tools and are the same tools that major chip makers use to build commercial chips. As such they are very powerful tools but they aren't necessarily intuitive to use. They are very efficient tools for the power user, but they sometimes have a steep learning curve. We'll mostly use the schematic capture and Verilog simulation portions of the tools. Individual projects may choose to use the integrated circuit layout portions, but this will not be required.

I've written a book about using the Cadence and Synopsys tools. It's not required for the course, but I think it's an extrememly useful reference when you use the tools (and cheap as textbooks go...). If you want to, you can purchase the book through Amazon or other on-line booksellers. I'll put the first few chapters on-line for this class. These are draft chapters, but they're very similar to the published chapters. Please respect these files and don't copy them or let them escape out to the web. The chapters will be available only from the utah.edu web domain. You are, of course, also free to read the CAD tool documentation and learn more right from the source. However, I encourage you to start with the Lab Manual because I know that using the tools in this way works. If you discover some new trick about using the tools, I'd love to hear about it!

 

The following draft book chapters are in PDF format:

Here's a good chapter from another book

Assignments

  • Review assignment. In PDF. This assignment is a self-assesment assignment. It won't be graded You should take this exam and try to do it without looking at other course material. If you can answer all the questions then you have the right background for this course. If you can't, you will need to brush up on some of your digital logic background! Please take this seriously! If you have trouble with this exam, you will also have trouble with the project!

  • Information about CADE electronic handin can be found here in PDF

  • CAD1: Cadence Schematic Capture and Simulation, Due Tuesday, January 25th, 5:00pm
    Note - if you've taken 6710 or 6720 this will be a total review, but please do it anyway to make sure we're all using the same Cadence setup.
  • CAD2: Timing in Verilog/Spectre simulations plus problems from Chapter 1. Due Tuesday, February 8th, 11:59pm
  • CAD3: Prefix adder design and measurement Due Tuesday, February 22nd, 11:59pm
  • CAD4: Reduction by rows and columns Due Thursday, March 3rd, 5:00pm
  • CAD5: Power measurement and multipliers Due Tuesday March 29. The AddTest.v testbench file can be found here.
  • CAD6: Final Project. You can choose your own project or choose one of the projects I've described. You should turn in a short (1-2 page) project proposal by Tuesday, April 12th. The final project is Due on Tuesday May 3rd.

     

    Helpful Info

    There's a lot of good info on the CS/EE 5710/6710 Digital VLSI class web site that you might want to look at.

    Look in the Tool Information part of that web site for useful info about Verilog, for example. There are some quick reference guides and tutorials that can give you good information about Verilog as a language.

    Here's information about using VNC to run the tools remotely courtesy of Mike Lodder from a few years ago. Using VNC to display the cade desktop through the network on your home machine is much faster than direct X11 tunnelling of the Cadence tools to your desktop X server...

     

    Slides