CS/ECE 6712: VLSI Testing
- Instructor: Erik Brunvand,
email@example.com, MEB 3142, 581-4345
- Class: W 1:25-2:45 in MEB 3105
- We'll meet only occasionally in the beginning of the semester to talk about how to generate tests for you chips. After that teams will work on
their own to develop tests for their chips that are being fabricated. We'll
schedule regular meetings between the groups and the instructor to
- As the semester progresses we'll schedule training sessions on the tester for each group using a tutorial circuit.
- Prerequisites: Having a chip submitted to MOSIS for fabrication.
- Textbook: None. I'll hand out documents about testing, and
about using the Tektronix LV500 chip tester hardware.
- Mailing List:
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This course is for people who have submitted a VLSI chip for
fabrication through MOSIS. Students will prepare tests for their
chips, convert those tests into a format suitable for our chip tester,
and use the Tektronix LV500 chip tester to test their chips when they
are returned from MOSIS. MOSIS requires that all educational chips be
tested and that a test report is returned to MOSIS. This is one
primary goal of this course: to test your chip, write a test report,
and send that report to MOSIS.
Teams may also want to design boards to host their chips in a small
system. Prototypes can be designed using wire-wrap technology, or with printed
circuit boards. After testing the chip in the tester, working chips can be
integrated into a prototype system.
- Slides describing the procedure for preparing a chip for fabrication two slides to a page in PDF
- Slides introducing the LV500 chip tester two slides to a page in PDF.
- THe "DUTmap" is a file with a list of how the5710/6710 PGA pacakge pins map to the tester
sector.channel assignments. We have two testers that each require a different mapping of pins to the test cards:
- Examples of .msa tester setup files can also be found in
in this directory
- Bonding diagrams for chips are here in PDF